? semiconductor components industries, llc, 2001 october, 2001 rev. 1 1 publication order number: sn74ls161a/d sn74ls161a, sn74ls163a bcd decade counters/ 4-bit binary counters the ls161a/163a are high-speed 4-bit synchronous counters. they are edge-triggered, synchronously presettable, and cascadable msi building blocks for counting, memory addressing, frequency division and other applications. the ls161a and ls163a count modulo 16 (binary). the ls161a has an asynchronous master reset (clear) input that overrides, and is independent of, the clock and all other control inputs. the ls163a has a synchronous reset (clear) input that overrides all other control inputs, but is active only during the rising clock edge. binary (modulo 16) asynchronous reset ls161a synchronous reset ls163a ? synchronous counting and loading ? two count enable inputs for high speed synchronous expansion ? terminal count fully decoded ? edge-triggered operation ? typical count rate of 35 mhz ? esd > 3500 volts guaranteed operating ranges symbol parameter min typ max unit v cc supply voltage 4.75 5.0 5.25 v t a operating ambient temperature range 0 25 70 c i oh output current high 0.4 ma i ol output current low 8.0 ma low power schottky soic d suffix case 751b plastic n suffix case 648 16 1 16 1 soeiaj m suffix case 966 16 1 device package shipping ordering information sn74ls161an 16 pin dip 2000 units/box sn74ls161ad soic16 38 units/rail sn74ls161adr2 soic16 2500/tape & reel sn74ls161am soeiaj16 see note 1 sn74ls161amel soeiaj16 1. for ordering information on the eiaj version of the soic package, please contact your local on semiconductor representative. see note 1 http://onsemi.com 16 pin dip 2000 units/box sn74ls163ad soic16 38 units/rail sn74ls163adr2 soic16 2500/tape & reel sn74ls163am soeiaj16 see note 1 sn74ls163amel soeiaj16 see note 1 sn74ls163an
sn74ls161a, sn74ls163a http://onsemi.com 2 connection diagram dip (top view) parallel enable (active low) input parallel inputs count enable parallel input count enable trickle input clock (active high going edge) input master reset (active low) input synchronous reset (active low) input parallel outputs terminal count output pe p 0 - p 3 cep cet cp mr sr q 0 - q 3 tc 1.0 u.l. 0.5 u.l. 0.5 u.l. 1.0 u.l. 0.5 u.l. 0.5 u.l. 1.0 u.l. 10 u.l. 10 u.l. 0.5 u.l. 0.25 u.l. 0.25 u.l. 0.5 u.l. 0.25 u.l. 0.25 u.l. 0.5 u.l. 5 u.l. 5 u.l. notes: a) 1 ttl unit load (u.l.) = 40 a high/1.6 ma low. high low (note a) loading pin names v cc = pin 16 gnd = pin 8 logic symbol note: the flatpak version has the same pinouts (connection diagram) as the dual inline package. 14 13 12 11 10 9 123456 7 16 15 8 v cc *r tc q 0 q 1 q 2 cet q 3 pe cp p 0 p 1 p 2 p 3 cep gnd 934 56 7 10 2 15 114131211 pe p 0 p 1 p 2 p 3 cep cet cp *r q 0 q 1 q 2 q 3 tc *mr for ls161a *sr for ls163a *mr for ls161a *sr for ls163a
sn74ls161a, sn74ls163a http://onsemi.com 3 ls161a ? ls163a 0123 4 5 6 7 8 9 10 11 12 13 14 15 count enable = cep ? cet ? pe tc for ls161a & ls163a = cet ? q 0 ? q 1 ? q 2 ? q 3 preset = pe ? cp + (rising clock edge) reset = mr (ls161a) reset = sr ? cp + (rising clock edge) reset = (ls163a) state diagram logic equations functional description the ls161a/163a are 4-bit synchronous counters with a synchronous parallel enable (load) feature. the counters consist of four edge-triggered d flip-flops with the appropriate data routing networks feeding the d inputs. all changes of the q outputs (except due to the asynchronous master reset in the ls161a) occur as a result of, and synchronous with, the low to high transition of the clock input (cp). as long as the set-up time requirements are met, there are no special timing or activity constraints on any of the mode control or data inputs. three control inputs e parallel enable (pe ), count enable parallel (cep) and count enable trickle (cet) e select the mode of operation as shown in the tables below. the count mode is enabled when the cep, cet, and pe inputs are high. when the pe is low, the counters will synchronously load the data from the parallel inputs into the flip-flops on the low to high transition of the clock. either the cep or cet can be used to inhibit the count sequence. w ith the pe held high, a low on either the cep or cet inputs at least one set-up time prior to the low to high clock transition will cause the existing output states to be retained. the and feature of the two count enable inputs (cet ? cep) allows synchronous cascading without external gating and without delay accumulation over any practical number of bits or digits. the terminal count (tc) output is high when the count enable trickle (cet) input is high while the counter is in its maximum count state (hllh for the bcd counters, hhhh for the binary counters). note that tc is fully decoded and will, therefore, be high only for one count state. the ls161a and ls163a count modulo 16 following a binary sequence. they generate a tc when the cet input is high while the counter is in state 15 (hhhh). from this state they increment to state 0 (llll). the master reset (mr ) of the ls161a is asynchronous. when the mr is low, it overrides all other input conditions and sets the outputs low. the mr pin should never be left open. if not used, the mr pin should be tied through a resistor to v cc , or to a gate output which is permanently set to a high logic level. the active low synchronous reset (sr ) input of the ls163a acts as an edge-triggered control input, overriding cet, cep and pe , and resetting the four counter flip-flops on the low to high transition of the clock. this simplifies the design from race-free logic controlled reset circuits, e.g., to reset the counter synchronously after reaching a predetermined value. mode select table *sr pe cet cep action on the rising clock edge ( ) l x x x reset (clear) h l x x load (p n q n ) h h h h count (increment) h h l x no change (hold) h h x l no change (hold) *for the ls163a only. h = high voltage level l = low voltage level x = don't care
sn74ls161a, sn74ls163a http://onsemi.com 4 ls161a dc characteristics over operating temperature range (unless otherwise specified) limits symbol parameter min typ max unit test conditions v ih input high voltage 2.0 v guaranteed input high voltage for all inputs v il input low voltage 0.8 v guaranteed input low voltage for all inputs v ik input clamp diode voltage 0.65 1.5 v v cc = min, i in = 18 ma v oh output high voltage 2.7 3.5 v v cc = min, i oh = max, v in = v ih or v il per truth table v output low voltage 0.25 0.4 v i ol = 4.0 ma v cc = v cc min, v in v il or v ih v ol output low voltage 0.35 0.5 v i ol = 8.0 ma v in = v il or v ih per truth table i ih input high current mr , data, cep, clock pe , cet 20 40 m a v cc = max, v in = 2.7 v i ih mr , data, cep, clock pe , cet 0.1 0.2 ma v cc = max, v in = 7.0 v i il input low current mr , data, cep, clock pe , cet 0.4 0.8 ma v cc = max, v in = 0.4 v i os short circuit current (note 2) 20 100 ma v cc = max i cc power supply current total, output high total, output low 31 32 ma v cc = max 2. not more than one output should be shorted at a time, nor for more than 1 second. ls163a dc characteristics over operating temperature range (unless otherwise specified) limits symbol parameter min typ max unit test conditions v ih input high voltage 2.0 v guaranteed input high voltage for all inputs v il input low voltage 0.8 v guaranteed input low voltage for all inputs v ik input clamp diode voltage 0.65 1.5 v v cc = min, i in = 18 ma v oh output high voltage 2.7 3.5 v v cc = min, i oh = max, v in = v ih or v il per truth table v output low voltage 0.25 0.4 v i ol = 4.0 ma v cc = v cc min, v in v il or v ih v ol output low voltage 0.35 0.5 v i ol = 8.0 ma v in = v il or v ih per truth table i ih input high current data, cep, clock pe , cet, sr 20 40 m a v cc = max, v in = 2.7 v i ih data, cep, clock pe , cet, sr 0.1 0.2 ma v cc = max, v in = 7.0 v i il input low current data, cep, clock, pe , sr cet 0.4 0.8 ma v cc = max, v in = 0.4 v i os short circuit current (note 3) 20 100 ma v cc = max i cc power supply current total, output high total, output low 31 32 ma v cc = max 3. not more than one output should be shorted at a time, nor for more than 1 second. ac characteristics (t a = 25 c)
sn74ls161a, sn74ls163a http://onsemi.com 5 limits symbol parameter min typ max unit test conditions f max maximum clock frequency 25 32 mhz t plh t phl propagation delay clock to tc 20 18 35 35 ns t plh t phl propagation delay clock to q 13 18 24 27 ns v cc = 5.0 v c l = 15 pf t plh t phl propagation delay cet to tc 9.0 9.0 14 14 ns l t phl mr or sr to q 20 28 ns ac setup requirements (t a = 25 c) limits symbol parameter min typ max unit test conditions t w cp clock pulse width low 25 ns t w mr or sr pulse width 20 ns t s setup time, other* 20 ns t s setup time pe or sr 25 ns v cc = 5.0 v t h hold time, data 3 ns v cc 5 . 0 v t h hold time, other 0 ns t rec recovery time mr to cp 15 ns *cep, cet, or data definition of terms setup time (t s ) e is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from low to high in order to be recognized and transferred to the outputs. hold time (t h ) e is defined as the minimum time following the clock transition from low to high that the logic level must be maintained at the input in order to ensure continued recognition. a negative hold time indicates that the correct logic level may be released prior to the clock transition from low to high and still be recognized. recovery time (t rec ) e is defined as the minimum time required between the end of the reset pulse and the clock transition from low to high in order to recognize and transfer high data to the q outputs. ac waveforms figure 1. clock to output delays, count frequency, and clock pulse width figure 2. master reset to output delay, master reset pulse width, and master reset recovery time 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v cp q t w (h) t w (l) t rec t phl t phl t plh other conditions: pe = mr (sr ) = h cep = cet = h other conditions: pe = l p 0 = p 1 = p 2 = p 3 = h t w q 0 q 1 q 2 q 3 mr cp
sn74ls161a, sn74ls163a http://onsemi.com 6 figure 3. the positive tc pulse occurs when the outputs are in the (q 0 ? q 1 ? q 2 ? q 3 ) state for the ls161 and ls163. other conditions: cp = pe = cep = mr = h 1.3 v t phl t plh 1.3 v 1.3 v 1.3 v cet tc ac waveforms (continued) the positive tc pulse is coincident with the output state (q 0 ? q 1 ? q 2 ? q 3 ) for the ls161 and ls163. figure 4. other conditions: pe = cep = cet = mr = h 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v t plh t phl cp tc the shaded areas indicate when the input is permitted to change for predictable output performance. figure 5. 1.3 v 1.3 v other conditions: pe = l, mr = h cp 1.3 v 1.3 v 1.3 v t s (h) t s (l) t h (h) = 0 t h (l) = 0 q 0 q 1 q 2 q 3 p 0 p 1 p 2 p 3 other conditions: pe = h, mr = h 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v t s (h) t s (l) t h (h) = 0 t h (l) = 0 t s (h) t h (h) = 0 t s (l) t h (l) = 0 count hold hold cep cp cet q cp sr or pe q response to pe reset count or load q response to sr parallel load (see fig. 5) count mode (see fig. 7) t s (l) t s (h) t h (l) = 0 t h (h) = 0 1.3 v 1.3 v figure 6. count enable trickle input to terminal count output delays clock to terminal count delays setup time (t s ) and hold time (t h ) for parallel data inputs setup time (t s ) and hold time (t h ) for count enable (cep) and (cet) and parallel enable (pe ) inputs figure 7. the shaded areas indicate when the input is permitted to change for predictable output performance. 1.3 v
sn74ls161a, sn74ls163a http://onsemi.com 7 package dimensions n suffix plastic package case 64808 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 d suffix plastic soic package case 751b05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
sn74ls161a, sn74ls163a http://onsemi.com 8 package dimensions h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z m suffix soeiaj package case 96601 issue o on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. sn74ls161a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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